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CyberWorkBench

CyberWorkBench is NEC’s C-based integrated environment for System LSI design. It has all the tools needed for efficient C-based design: a behavioral synthesizer, simulator, and formal verifier.

Best-in-class Behavioral Synthesis: CWB generates RTL from ANSI-C or SystemC. CWB has one of the largest language support coverage. It accepts all data types including arrays, structures and pointers.

Also any control structure achieving RTL comparable to hand coded RTL.CWB can be used by professional ASIC designers that need fine synthesis controllability and FPGA designers without extensive hardware knowledge. CWB has one of the most comprehensive and rich synthesis controllability ranging from global synthesis options to local synthesis directives in the form of pragmas without having the need to modify the original C source code.

CWB GUI shows various metrics such as area, latency, delay, wire, routability. Also, GUI provide several windows showing I/O, register and memory access , state transition, datapath diagram which can show critical paths, false path information, C-RTL cross probing and so on. These analysis reports help designer to find good architecture without running logic synthesis and RTL simulation.

For un-experienced designers CWB provides and automatic design space exploration utility to explore these synthesis options in order to quickly and easily explores multiple hardware implementations with different area vs. performance characteristics. Even software designers can benefit from CWB’s strengths due to its powerful dual synthesis engine.

  • SoC level design capability: CWB includes SoC level design capabilities, being able to simulate and synthesis complete SoCs not just individual IPs. CPU buses such as AMBA AHB or AXI are automatically generated using CWB’s bus interface generator tool. Also I/F circuits can be described and synthesized efficiently in CWB. Moreover legacy RTL or RTL IPs can be co-simulated with the newly generated C/SystemC code by creating C models for these RTL blocks. Arrays can be mapped to any type of memories (SRAM, DRAM) as well as registers. CWB generates the interface and decoder automatically for all of them. For the pin-to-pin communication, our “top module generator” interconnects all modules automatically. CWB supports behaviorally hierarchical synthesis. The behavioral synthesized circuit, or legacy RTL, gate circuits can be called as a function in their parent function in C.
  • Behavioral IP (Cyberware): CWB comes with an extensive set of highly parametrizable behavioral IPs. Different designs optimized for frequency, area, power, throughput or latency can be easily generated. Some of these IPs are: AES, DES, RSA, Viterbi decoder and arithmetic operations. Contact us for more information about our IP library.
  • C-level verification: CWB allows the full verification and validation of the design at the C-level in includes static and dynamic verification tools. Designers no longer need to design in C and verify the RTL.
  • Formal verification. CWB comes with a formal verifier that allows to statically without the need to run any simulation to verify the RTL at the C-level. In CWB they specify immediate assertions at the C-code and CWB verifies the RTL indicating the C-code assertion proved. Global properties can be specified with PSL and customizable GUI template.
  • High speed simulation: CWB comes with behavioral bit accurate simulation model and cycle accurate model generators. C++ and SystemC models can be compiled with g++ and executed as a binary, which runs several 10~100X faster than synthesizable RTL simulation. Also, cycle accurate VerilogHDL model is generated, which also runs 10~100x faster than synthesizable RTL.
    Cycle accurate model allows to co-simulate HW and SW, also simulation with Matlab/simlnk.
  • Source code debugging capability: CWB comes with a source code debugger that allows the debugging the RTL looking at the untimed or timed C-code. With this utility it is not necessary to debug the RTL anymore. CWB’s source code debugger shows the value of variables in C and registers in RTL at all time. They can be saved as vcd or fsdb, vpd, shm file according to your simulator to observe the cycle/timing of the synthesized circuits.
  • RTL Testbench Generator: CWB’s testbench generator automatically creates a testbench for major RTL simulators (Modelsim, VCS, Incisive) which can read test patterns for behavioral simulation. This allows the comparison between the software’s golden output with the RTL simulation output.
  • CWB support all ASIC libraries and FPGA
    DSP macros in FPGA and designwares in ASIC also supported.

CyberWorkBench is a complete tool suite for C/SystemC VLSI design and verification. Once you start using CWB you will never have the need to design in RTL anymore.

CyberWorkBenchCyberWorkBench Overview

All the tools listed in Fig. 1 work together in NEC’s CyberWorkBench integrated design environment, for easy synthesis, analysis and verification.

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