IP Design Service

The process of designing analog circuit components in the mixed signal IC design involves highly complex boundary conditions in terms of design and technology. Today’s level of automation in this area is still very low and renders developments susceptible to errors, difficult to reproduce and offers only few options for reuse.

Chip photo and block diagram for SMART Sensor ASIC – the green components developed as intelligent IP

Chip photo and block diagram for SMART
Sensor ASIC – the green components developed as intelligent IP

For its services in the development of mixed signal hard IPs in a variety of integrated technologies, Fraunhofer IIS/EAS uses innovative and custom-developed processes for automation. One of these processes is the Intelligent IP Design Flow (IIP Design Flow) – a practical and holistic approach for the complex work of designing analog components. With this approach, developers at Fraunhofer IIS/EAS were able to show significant time and effort savings in several design projects. First IIP modules for customers will be available by the end of 2016.

List of hard IP blocks offered by Fraunhofer IIS/EAS

ADC Type Resolution Conversion Rate Technology Node
ADC16b013kS180nm cyclic 16 bit 13 kS/s 180 nm
ADC12b017kS180nm cyclic 12 bit 17 kS/s 180 nm
ADC12b054kS180nm cyclic 12 bit 54 kS/s 180 nm
ADC12b020MS350nm pipeline 12 bit 20 kS/s 350 nm


IIP design flow concept

IIP design flow concept

Take advantage of many years of experience in designing circuits in the most varied technologies of numerous foundries from 0.6 µm to 28 nm. Profit at the same time from increased reliability of design and reduced development time.

ASIC with a high-resolution A/D converter (12-bit 20MSps ADC)

ASIC with a high-resolution A/D converter (12-bit 20MSps ADC)


  • Reliable and sustainable design service for mixed signal ICs with broad technology portfolio
  • Design reliability thanks to automated, flexible IP components
  • Shorter development times with focus on high quality
  • Circuit optimization at system, circuit layout and post-layout level
  • Technology transfer with new automation approaches (horizontal and vertical)


  • Design of customized mixed signal IPs and ASICs
  • Technology transfer and migration
  • Yield optimization (design for yield)
  • Rapid adaptation to change requests/ supply of IP variants
  • Reuse of existing circuit designs
  • Establishment of in-house, modular, automated component library

Download the Fraunhofer IIS/EAS IP Design Services Datasheet – CLICK HERE

To find out more about Fraunhofer IIS/EAS product offerings click one of the links below:

To send an email request for more information CLICK HERE

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