Product HiDFT-STAR v2.0

Key Features

• Support editing of Verilog, VHDL or mixed designs

• Design Rule Checks (DRC) on RTL input

• Flexible set of commands for design querying

• Comprehensive set of commands for incremental editing

• Multiple connection techniques

Change driver / load of arbitrary node in the design hierarchy

Create connectivity between arbitrary nodes in the design hierarchy

• Powerful tracing signal mechanism across the design hierarchy

• Effective mechanism for connectivity checking

• Easy development of custom Tcl applications

• Silicon proven on multiple designs

                          Datasheet

Overview

HiDFT-STAR (High level Design For Test – Structured Test ARchitectures) is a fully customizable RTL-to-RTL editing tool for IP cores and SOC blocks. HiDFT-STAR works seamlessly with the RTL testability sign-off solution and helps automating the integration process at RTL.

HiDFT-STAR has shown effectiveness in moving DFT implementation tasks from gate to RTL. This silicon proven product has successfully helped moving the integration of memory BIST test logic from gate to RTL. The main benefit is a significant reduction of TAT (Turn Around Time) because of the reactivity which is brought by new RTL-to-RTL editing capabilities.